The present invention relates to fabrication of a semiconductor device. More particularly, the present invention relates to a CMOS (complementary metal oxide semiconductor) device wherein p-channel and n-channel MOS (metal oxide semiconductor) transistors are formed on a same substrate. The present invention also relates to a method for fabricating this CMOS device.
With the recent improvement in semiconductor fabricating apparatuses such as photo and etching equipments, MOS (metal oxide semiconductor) devices may be designed and fabricated to be less than submicron or sub-half micron in size. It is, however, difficult to easily control a channel length of 0.1 to 0.2 mm by using conventional equipment. As the channel of a MOS transistor becomes shorter and shorter, this increases the hot-carrier effect on the channel.
FIGS. 1A through 1C show a conventional process steps of fabricating a typical MOS transistor with a lightly doped drain (LDD) structure.
Referring to FIG. 1A, a gate oxide layer 12 and a gate 13 are sequentially formed on a p-type semiconductor substrate 11. A lightly doped source/drain region 15 is then formed in the substrate 1 using ion implantation with the gate 13 as a mask.
As shown in FIG. 1B, after an insulating layer 16 is formed over the substrate, an anisotropic etching is carried out to selectively remove the insulating layer 16. As a result, a spacer 17 is formed on both sidewalls of the gate 13, as shown in FIG. 1C.
Subsequently, ion implantation using n.sup.+ -type impurity ions as dopants is carried out to form an n.sup.+ -type source/drain region 19, as shown in FIG. 1C. During this ion implantation, the gate 13 and the spacer 17 serve as a mask. Therefore, an LDD structure can be formed.
Conventional MOS transistors having the above LDD structure may restrain an hot-carrier effect occurring due to the short-channel of the MOS transistor. But, as a CMOS device becomes smaller and smaller, approaching less than a half-micron or sub-half micron in size, each channel length of MOS transistors therein becomes shorter. This raises serious problems that it is both impossible to completely restrain the occurrence of a hot-carrier effect in the CMOS device and it is difficult to fabricate MOS transistors having a channel length of about 0.1 mm and less because of the practical processing limitation of a photo equipment.